To break the status quo, the PulseRain Reindeer takes a different approach called 'hold and load', which brings a hardware based OCD (on-chip debugger) into the fore, as illustrated below: In other words, the soft CPU might have to improvise a little bit to work on various platforms. And when it comes to SoC + FPGA, like the Microsemi Smartfusion2, a hardcore processor could also be involved in the boot-loading. The boot loader itself could be executed in place, or loaded with a small preloader implemented in FPGA fabric.

For some FPGAs, like Intel Cyclone or Xilinx Artix, the memory initial data can be stored in FPGA bitstream, but other platforms might choose to use external flash for the ROM data. The implementation of ROM is not consistent across all FPGA platforms.The bootloader will be more or less intrusive, as it takes memory spaces.And the PC will be set to the _start address of the new image afterwards. After power on reset, the boot loader is supposed to be executed first, for which it will move the rest of the code/data into RAM.The traditional approach is more or less like the following: Highlights - Hold and Loadīootstrapping a soft CPU tends to be a headache. And those platforms will find themselves a good match with the PulseRain Reindeer when it comes to soft CPU.

Some FPGA platforms, like the Lattice iCE40 UltraPlus family, carry a large amount of SPRAM with very little EBR RAM. Thanks to using single port memory to store both code and data, the Reindeer soft CPU is quite portable and flexible across all FPGA platforms. In this way, the Instruction Fetch and Memory Access always happen on different clock cycles, thus to avoid the structural hazard caused by the single port memory. For the even cycle, only IF and IE stages are active, while for the odd cycle, only ID and MEM stages are active. In the 2 x 2 layout, each stage is active every other clock cycle.

However, unlike traditional pipelines, Reindeer's pipeline stages are mapped to a 2 x 2 layout, as illustrated below: Register Write Back and Memory Access (MEM).Reindeer's pipeline is composed of 4 stages: It strives to make a balance between speed and area, and offers a flexible choice for soft CPU across all FPGA platforms. It supports RISC-V RV32I instruction set, and features a 2 x 2 pipeline. PulseRain Reindeer is a soft CPU of Von Neumann architecture. PulseRain Reindeer - RISCV RV32I Soft CPU

Lattice fpga simulation